As a senior physical designer you will develop highly automated design flows to reduce the barrier to silicon for everyone.
Responsibilities
Lead the development of state of the art automated physical design methodologies.
Lead back-end SoC implementation efforts from RTL to tapeout/packaging.
Work effectively with RTL design team, firmware team, and customers on agile SoC development projects.
Requirements
BS in EE/CE and 5+ years of experience (or equivalent) in SoC physical design.
Experience with multiple successful commercial tapeouts at advanced process nodes(16nm and below required, 7nm or smaller preferred).
Strong working knowledge of back-end tools and flows – floor planning, P&R, timing, power, EMIR, DFM, DFT, clocking, power grid analysis, thermal, physical verification, synthesis, and sign-off.
Experience with integration of complex high speed 3rd party mixed signal IP.
Strong programming and scripting skills (TCL, Python).
Strong communication skills.
Highly creative and self-driven.