Join the Chip Design Revolution
At Zero ASIC our mission is to revolutionize silicon system design. If you are looking to really make a difference, you should considering joining us. There is no other company in the industry quite like it!
Shipping Custom Silicon in Hours, Not Years
Standardized chiplets
First demonstration of fully standardized chiplets, supporting O(m^n) system permutations (m=library size, n=substrate sockets).
Smart substrates
Active 3D silicon substrates that decouple compute and networking, enabling a standardized "building blocks" approach to system composition.
World-leading energy efficiency
Sub 0.1 pj/bit chiplet communication efficiency.
Highlights from our Blog
View all updates »Zero ASIC announces release of Platypus heterogeneous eFPGA
Today Zero ASIC announces the release of a new set of breakthrough open standard eFPGA cores with an advanced set of embedded BRAM and DSPs.
Zero ASIC releases Wildebeest, the world's highest performance FPGA synthesis tool.
Cambridge, MA – September 17, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of WildebeestTM, the world's highest performance open source FPGA synthesis tool. Wildebeest is the first open source logic synthesis solution with Quality of Results (QoR) comparable to proprietary vendor locked tools.
Open-source static timing analysis for FPGAs
Today Zero ASIC is announcing availability of a production-grade, open-source static timing analysis (STA) flow for FPGAs, enabling analysis of complex multi-clock designs for the open-source FPGA design community.