EFABRIC
Introduction
The EFABRIC is an active silicon interposer integrating networking functionality, 3D CLINK chiplet interfaces, and 2D UCIe chiplet interfaces.
Block diagram
Core Features
- Network-On-Interposer
- 4 Tbps aggregate bisection bandwidth
- 64 in-order dual-issue RISC-V CPU cores
- 16 MB distributed SRAM
- Up to 1GHz operating frequency
- <0.1 pJ/bit 3D link energy efficiency
Connectivity Features
Protocol | Quantity |
---|
CLINK 3D links (128 Gbps) | 64 |
UCIE 2D links (128 Gbps) | 32 |
GPIO | 256 |
UART | 16 |
I2C | 16 |
SDIO | 16 |
SPI | 16 |
QSPI | 16 |
PWM | 16 |
ETH 10/100/1000 | 4 |
JTAG | 1 |
Chiplet Dimensions
Status & Availability
Stage | Status |
---|
Emulation (partial) | Available |
Test Chip | Q1, 2024 |
Device Sampling | Q3, 2024 |