Today Zero ASIC is announcing availability of a production-grade, open-source static timing analysis (STA) flow for FPGAs, enabling analysis of complex multi-clock designs for the open-source FPGA design community.
Today I had the pleasure of giving a talk at the CHISIC (Chiplets Solutions for Custom IC Design) workshop in Boston. CHISIC focuses on providing insights and solutions related to chiplet technology and its application in custom IC design, specifically targeting the field of artificial intelligence. The workshop aims to help attendees learn about the latest advancements in chiplet architectures, connectivity, and associated design challenges.
Cambridge, MA – March 18, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced PlatypusTM, the world's first open standard eFPGA product. Platypus addresses a long standing critical issue of FPGA obsolescence and vendor lock that has put critical infrastructure at risk.
The GOMACTech conference was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for government reviews.
To shed light on the state of open source chip design tools, Zero ASIC has created the open source Silicon Compiler dashboard.
Barring natural (and unnatural) disaster, Zero ASIC has just secured funding for the next 5 years!
The topic of my panel presentation was "mechanical reconfigurability". We have been going around and around the grand flexibility challenge for 30 years now, trading off performance vs flexibility (CPU vs FPGA vs CGRA vs ASIC vs GPU vs TPU vs ASP vs BLAH-BLAH). The design exploration space is getting boring, you can't have your cake and eat it too. In my view, the only practical escape path is mechanical reconfigurability. Like just in time compilation, but for hardware.
WOSET is one of the few workshops dedicated to open source EDA. I had the honor of giving the CEDA keynote at the first WOSET conference in 2019. This year, I had the opportunity to stand in for Steven Herbst to present our recent work on cloud based wafer-scale emulation. We presented Switchboard at WOSET-24, successfully demonstrating RTL simulation of a million-core system on thousands of cloud compute cores. The total time to build the design and simulate a distributed matrix multiplication was under 15 minutes, demonstrating the agility of our approach.
The DoE sponsored 2024 Workshop on Basic Research Needs for Energy-Efficient Computing for Science will identify priority research directions in energy-efficient computing for science.
Zero ASIC is excited to be part of the University of Texas at Austin led team developing the next generation of high-performing semiconductor microsystems for the Department of Defense.
Presenting the open source Switchboard project at Latch-Up 2024
Presenting the open source UMI protocol at Latch-Up 2024
Zero ASIC proudly announces Logik, a lightweight open source FPGA RTL-to-bitstream flow powered by Zero ASIC's Silicon Compiler solution for circuit design automation flow control. Logik enables users to generate bitstreams for FPGAs with a Python-driven, single execution step by sequencing the execution of multiple open source tools in an FPGA CAD tool chain. To demonstrate Logik's capabilities, Zero ASIC has distributed a sample eFPGA architecture of their own design for which users can generate bitstreams and simulate in the cloud using Zero ASIC's digital twin platform.
Want to help change the trajectory of semiconductor and AI? Take one minute to fill out this survey to tell us what chiplets the community should focus on.
Composable chiplets represent a powerful new design approach with the potential of disrupting a large portion of the semiconductor market. This month I will be presenting ideas for how chiplets can be applied to a number of critical applications.
Today, Zero ASIC is releasing a demo that shows how to create a custom EBRICK, a chiplet that can plug into our SiP design ecosystem. The demo can be found on GitHub.
Chiplets are all the rage these days, even making MIT Technology Review's 10 Breakthrough Technologies of 2024. This is pretty incredible for such a niche technology! Unfortunately, as of today chiplets are only accessible to semiconductor mega-corps. To unlock the true power of disaggregated chiplet innovation, we need to drastically reduce the barriers to chiplet based design.
We are pleased to announce the open source release of zaui, our npm-installable SvelteKit toolchain for building websites from markdown.
Zero ASIC is thrilled to announce Switchboard, a high-performance open-source framework for communication between RTL simulations, FPGA emulations, Python, and C++. Switchboard makes it possible to simulate large hardware systems in a distributed fashion, using a wide variety of model types, and to interact with the modeled systems from popular software languages.
Do you think chiplets are tasty? I think I’ve just seen the future of chiplet-based design—well, one possible future—and it looks finger-licking good to me. Just to make sure we are all tap-dancing to the same skirl of the bagpipes, let’s start by setting the scene. For the purposes of these discussions, we will take the term integrated circuit (IC) to refer to a honking big ASIC, ASSP, SoC… that sort of thing.
Zero ASIC, a semiconductor startup, today came out of stealth to announce early access to its one-of-a-kind design and emulation platform, demonstrating a number of world firsts.
I gave an invited talk on reducing the barrier to chiplets at the DoE organized workshop, Chiplets for HPC and Advanced Sensors
Continued U.S. leadership in emerging technology requires a sustainable supply of advanced chips to power innovation from artificial intelligence to quantum computing. The CHIPS and Science Act, passed last year, aims to boost domestic research and manufacturing capacity for critical microelectronics.
Even with such subsidies, assembling all the elements required to reduce U.S. dependence on Asian companies “is a huge challenge,” said Andreas Olofsson, who ran a Defense Department research effort in the field before founding a packaging start-up called Zero ASIC. “You don’t have suppliers. You don’t have a work force. You don’t have equipment. You have to sort of start from scratch.”
Presenting the open source SiliconCompiler project at Latchup 2023?
Some of you may have been wondering why things have been quiet at ZeroASIC? The answer is that we have been busy working! I am very excited to tell you that we have now taped out 3 different homegrown chiplet designs in an advanced FinFET node
The biggest barrier to the democratization of chiplets is the availability and adoption of a common standard. We need a "USB/PCIE/I2C/ethernet/..." for chiplets! At Zero ASIC we are committed to promoting open standards. Today I am happy to tell you that we have joined the UCIe industry group to help reduce the barrier to chiplet design and manufacturing!
At the 59th DAC, I had the pleasure of moderating a really interesting panel on the open source EDA.
Zero ASIC paper on silicon compilation included in DAC proceedings. DAC is the permier conference on EDA and chip design methodology.
The open source SiliconCompiler project we have been working on for a year is now officially live. I am so thankfully to my collaborators Noah Moroze and William Ransohoff for joining me on this journey! Check it out and tell me what you think. We soft launched over the weekend and at least the Twitterverse seemed to like it. We are at DAC in SF this week. If you are here, I hope to see you!
Microsoft and Qualcomm Technologies will lead the second phase of a Pentagon chip initiative designed to leverage U.S. microelectronics capabilities while securing its technology supply chain. Microsoft will head a team that includes Ansys, Applied Materials, BAE Systems, Battelle Memorial Institute, Cadence Design Systems, Cliosoft, Flex Logix, GlobalFoundries, Intel Federal, Raytheon Intelligence and Space, Siemens EDA, Synopsys, Tortuga Logic, and Zero ASIC.
My keynote titled "How to Fail at Codesign" at the ASCR Workshop on Reimagining Codeseign.
...Andreas Olofsson, founder of Zero ASIC, hoped to tease out some predictions: “How many chiplets will be incorporated into a single design by 2025?
SAN JOSE, Calif. — The U.S. will pour $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. The programs, involving 15 companies and more than 200 researchers, were described for the first time in a talk at the Design Automation Conference here.
Adapteva, which was founded in 2008 by Andreas Olofsson, is one of the beneficiaries of the CRAFT program and used that investment and the help with the masks to crank up the number of cores on its Epiphany massively parallel chips from 64 cores on the Epiphany-IV to a whopping 1,024 cores on the Epiphany-V – and did so on the shoestring budget that DARPA mandated.
FEATURE Adapteva, an upstart RISC processor and co-processor designer that has tried to break into the big-time with its Epiphany chips for the past several years, is sick and tired of the old way of trying to get design wins to fund its future development.
Not many people these days propose radically new ideas for microprocessors, a costly business with big, entrenched competitors. Andreas Olofsson is doing it anyway.
EE Times In the course of my travels around the world I have been fortunate enough to meet some truly great engineers. However, it's rare that I am completely blown away by someone on the engineering front. At least, this was true until I was introduced to Andreas Olofsson, president and architect of Adapteva Inc.