Zero ASIC - April 3, 2024

Zero ASIC Releases Logik, a simple and powerful open source FPGA toolchain

Zero ASIC proudly announces Logik, a lightweight open source FPGA RTL-to-bitstream flow powered by Zero ASIC's Silicon Compiler solution for circuit design automation flow control. Logik enables users to generate bitstreams for FPGAs with a Python-driven, single execution step by sequencing the execution of multiple open source tools in an FPGA CAD tool chain. To demonstrate Logik's capabilities, Zero ASIC has distributed a sample eFPGA architecture of their own design for which users can generate bitstreams and simulate in the cloud using Zero ASIC's digital twin platform.

Zero ASIC - March 25, 2024

The Big Chiplet Survey (2024)

Want to help change the trajectory of semiconductor and AI? Take one minute to fill out this survey to tell us what chiplets the community should focus on.

Andreas Olofsson - March 22, 2024

Composable chiplets

Composable chiplets represent a powerful new design approach with the potential of disrupting a large portion of the semiconductor market. This month I will be presenting ideas for how chiplets can be applied to a number of critical applications.

Zero ASIC - March 19, 2024

Bring Your Own RTL to Zero ASIC's Chiplet Ecosystem

Zero ASIC - February 5, 2024

Lowering the Barrier to Chiplets

Chiplets are all the rage these days, even making MIT Technology Review's 10 Breakthrough Technologies of 2024. This is pretty incredible for such a niche technology! Unfortunately, as of today chiplets are only accessible to semiconductor mega-corps. To unlock the true power of disaggregated chiplet innovation, we need to drastically reduce the barriers to chiplet based design.

Jürgen Leschner - December 10, 2023

Zaui, our npm-installable SvelteKit toolchain

We are pleased to announce the open source release of zaui, our npm-installable SvelteKit toolchain for building websites from markdown.

Zero ASIC - December 4, 2023

Switchboard, an Open Source High-Performance Communication Platform

Zero ASIC is thrilled to announce Switchboard, a high-performance open-source framework for communication between RTL simulations, FPGA emulations, Python, and C++. Switchboard makes it possible to simulate large hardware systems in a distributed fashion, using a wide variety of model types, and to interact with the modeled systems from popular software languages.

Zero ASIC - October 17, 2023

Zero ASIC Democratizing Chip Making

Zero ASIC, a semiconductor startup, today came out of stealth to announce early access to its one-of-a-kind design and emulation platform, demonstrating a number of world firsts.

Andreas Olofsson - August 15, 2023

Reducing the Barrier to Chiplets

I gave an invited talk on reducing the barrier to chiplets at the DoE organized workshop, Chiplets for HPC and Advanced Sensors

Microsoft - May 23, 2023

Cloud-based chip design for national security achieves key milestone

Continued U.S. leadership in emerging technology requires a sustainable supply of advanced chips to power innovation from artificial intelligence to quantum computing. The CHIPS and Science Act, passed last year, aims to boost domestic research and manufacturing capacity for critical microelectronics.

NY Times - May 11, 2023

U.S. Focuses on Invigorating ‘Chiplets’ to Stay Cutting-Edge in Tech

Even with such subsidies, assembling all the elements required to reduce U.S. dependence on Asian companies “is a huge challenge,” said Andreas Olofsson, who ran a Defense Department research effort in the field before founding a packaging start-up called Zero ASIC. “You don’t have suppliers. You don’t have a work force. You don’t have equipment. You have to sort of start from scratch.”

Zero ASIC - December 15, 2022

Zero ASIC completes FPGA, CPU, and SRAM testchips

Some of you may have been wondering why things have been quiet at ZeroASIC? The answer is that we have been busy working! I am very excited to tell you that we have now taped out 3 different homegrown chiplet designs in an advanced FinFET node

Zero ASIC - December 1, 2022

Zero ASIC joins UCIe Consortium

The biggest barrier to the democratization of chiplets is the availability and adoption of a common standard. We need a "USB/PCIE/I2C/ethernet/..." for chiplets! At Zero ASIC we are committed to promoting open standards. Today I am happy to tell you that we have joined the UCIe industry group to help reduce the barrier to chiplet design and manufacturing!

Andreas Olofsson - July 17, 2022

What is the future of Open Source?

At the 59th DAC, I had the pleasure of moderating a really interesting panel on the open source EDA.

Andreas Olofsson - July 7, 2022

A distributed approach to silicon compilation

Zero ASIC paper on silicon compilation included in DAC proceedings. DAC is the permier conference on EDA and chip design methodology.

Zero ASIC - December 4, 2021

SiliconCompiler Launch!

Zero ASIC launches free open source cloud based chip compiler.

EETimes - November 23, 2021

DoD Ramps Secure Chip Design Effort

Microsoft and Qualcomm Technologies will lead the second phase of a Pentagon chip initiative designed to leverage U.S. microelectronics capabilities while securing its technology supply chain. Microsoft will head a team that includes Ansys, Applied Materials, BAE Systems, Battelle Memorial Institute, Cadence Design Systems, Cliosoft, Flex Logix, GlobalFoundries, Intel Federal, Raytheon Intelligence and Space, Siemens EDA, Synopsys, Tortuga Logic, and Zero ASIC.

Andreas Olofsson - March 16, 2021

How to Fail at Codesign

My keynote titled "How to Fail at Codesign" at the ASCR Workshop on Reimagining Codeseign.

EETimes - March 16, 2021

More than Chiplets | Facebook Enters the Fray

...Andreas Olofsson, founder of Zero ASIC, hoped to tease out some predictions: “How many chiplets will be incorporated into a single design by 2025?

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