About Zero ASIC

Zero ASIC (Cambridge, MA) is a semiconductor startup developing the world’s first composable chiplet platform. If successful, we will democratize access to silicon by reducing the cost and time of ASIC development by a factor of 100X.

History

2025

• Shipped Wildebeest
• Shipped Platypus

2024

• DARPA NGMM 3DHI award
• DoE microelectronics award(s)
• Million-core emulation demo
• Ray Stata angel investment
• DoD RAMP Phase2 extension

2023

• Shipped chiplet emulation platform
• Shipped Universal Memory Interface
• Shipped Switchboard
• Shipped Logik
• Shipped Lambdalib
• 12nm RISC-V CPU chiplet tapeout
• Lockheed Martin Ventures investment

2022

• SiliconCompiler DAC Paper
• 12nm CPU,FPGA,SRAM chiplet tapeouts
• DoD chiplet platform award

2021

• DoD RAMP Cloud EDA Phase 2
• Shipped SiliconCompiler

2020

• DoD RAMP Cloud EDA Phase 1
• Adapteva renamed Zero ASIC

2017-2019

• Andreas Olofsson joins DARPA

2016

• 1024-core 16nm Epiphany-V tapeout

2015

• DARPA Epiphany-V 16nm seedling
• 5G base station Epiphany IP licensee

2014

• Parallella SBC general availability
• Open Compute Hackathon Winner

2013

• Ericsson Ventures Investment
• Shipped Parallella board
• Parallella Open Source Hardware
• Shipped Epiphany Open Source SDK

2012

• Shipped Epiphany OpenCL Compiler
• Parallella Kickstarter Campaign
• Sampled 64-core 28nm Epiphany-IV
• Demonstrated 50GFLOPS/W at 28nm
• Bridge financing

2011

• 64-core 28nm Epiphany-IV tapeout
• 16-core 65nm Epiphany-III launch

2010

• 16-core 65nm Epiphany-III tapeout
• 16-core 65nm Epiphany-II tapeout

2009

• BittWare Investment
• 16-core 65nm Epiphany-1 tapeout
• Epiphany NoC Invented

2008

• Epiphany ISA Invented
• Adapteva founded