About
Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon.
One Broadway, Cambridge, MA 02142
History
2024
- DARPA sub-awardee on $850M 3DHI NGMM program
- DoE sub-awardee on multiple microelectronics projects
- Switchboard million-core wafer-scale digital twin emulation
- Angel investment by Ray Stata
- DoD RAMP Phase2 extension award
2023
- Release of free chiplet emulation platform
- Universal Memory Interface (UMI) open sourced
- Switchboard emulation platform open sourced
- $2M investment by Lockheed Martin Ventures
2022
- SiliconCompiler DAC Paper
- DoD chiplet platform Phase1 contract
2021
2020
- DoD RAMP Cloud EDA Phase 1 award
- Adapteva renamed Zero ASIC
2017-2019
2016
2015
- DARPA Epiphany-V 16nm seedling
- Epiphany IP licenses to Tier 1 base station vendor
2014
2013
- $3.6M investment by Ericsson & Carmel Ventures
- Shipped first Parallella board
- Parallella SBC Hardware Open Sourced
- Epiphany CPU SDK Open Sourced
2012
- $900K Parallella Supercomputer Kickstarter Campaign
- 64-core 28nm Epiphany-IV sampled to customers
- First demonstration of 50GFLOPS/W at 28nm
- $850K bridge financing
2011
- 64-core 28nm Epiphany-IV tapeout
- 16-core 65nm Epiphany-III launch
2010
- 16-core 65nm Epiphany-III tapeout
- 16-core 65nm Epiphany-II tapeout
2009
- $1.5M investment by BittWare
- 16-core 65nm Epiphany-1 tapeout
- Epiphany NoC Invented
2008
- Epiphany ISA Invented
- Adapteva founded