About Zero ASIC
Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon.
History
2024
- DARPA NGMM 3DHI award
- DoE microelectronics awards
- Million-core digital twin emulation
- Ray Stata angel investment
- DoD RAMP Phase2 extension award
2023
- Shipped cloud-scale emulation platform
- Shipped Universal Memory Interface (UMI)
- Shipped Switchboard emulation platform
- Shipped Logik FPGA platform
- Shipped Lambdalib
- Tapeout of quad-core RISC-V 12nm test-chiplet
- Lockheed Martin Ventures investment
2022
- SiliconCompiler DAC Paper
- Tapeout of CPU, FPGA, & SRAM 12nm test-chiplets
- DoD chiplet platform award
2021
2020
- DoD RAMP Cloud EDA Phase 1
- Adapteva renamed Zero ASIC
2017-2019
2016
2015
- DARPA Epiphany-V 16nm seedling
- 5G base station Epiphany IP licensee
2014
2013
- Ericsson Ventures Investment
- Shipped Parallella board
- Parallella Open Source Hardware
- Epiphany CPU SDK Open Sourced
2012
- Parallella Kickstarter Campaign
- 64-core 28nm Epiphany-IV sampled to customers
- First demonstration of 50GFLOPS/W at 28nm
- Bridge financing
2011
- 64-core 28nm Epiphany-IV tapeout
- 16-core 65nm Epiphany-III launch
2010
- 16-core 65nm Epiphany-III tapeout
- 16-core 65nm Epiphany-II tapeout
2009
- BittWare Investment
- 16-core 65nm Epiphany-1 tapeout
- Epiphany NoC Invented
2008
- Epiphany ISA Invented
- Adapteva founded