We are always looking for outstanding new team members. If you think you can help us lower the barrier to silicon, we encourage you to send a resume and intro to firstname.lastname@example.org.
Zero ASIC does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. Zero ASIC is an equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status.
Director of Advanced Packaging
As the director of advanced packaging you will lead the development of heterogeneous system-in-package architectures and partnerships to address high volume and long tail manufacturing needs.
Lead the development of novel package architectures and manufacturing flows for the company’s heterogeneous system in package approach.
Work with OSATs and other partners to bring solutions from concept to high volume manufacturing .
Recruit and manage a team of internal individual contributors and external consultants to support high volume manufacturing.
Collaborate with the internal SoC design and architecture teams and external organization to define electrical, protocol, reliability, mechanical, and test standards for advanced packaging.
Collaborate with the SoC architecture and design team to converge on package architectures that
PhD or Master’s Degree in the technical subject area.
10+ years of experience in advanced semiconductor packaging
Experience with high volume SoC product manufacturing (>1M units)
Domain expertise in SoC reliability (ESD, EM, reliability, material compatibility, coplanarity controls, warpage mitigation, board interfaces).
Domain expertise in flip-chip, WLFO, 2.5D/3D, silicon interposers, advanced build up substrates, underfill, heatsinks, board.
Domain expertise in package signal integrity and power delivery,
Demonstrated success in low product cost optimization through appropriately constraining architecture, materials, vendors.
Strong ties to the advanced packaging industry community.
Outstanding collaboration skills
Senior Compiler Engineer
As a senior compiler engineer at Zero ASIC you will lead internal development of compiler infrastructure for our RISC-V based state of the art accelerators.
Lead the development of compilers for RISC-V based accelerators.
Collaborate with the hardware development team to optimize the architecture, working in a tight/agile hw/sw loop.
Develop early prototypes and present to potential system customers.
BS/MS or PhD in Computer Science or related field.
3+ years of industry experience (or equivalent academic research experience)
Demonstrated ability in building successful compilers for industry or research.
Hands-on experience with developing front-ends/back-ends for GCC or LLVM.
Experience with open source collaboration.
Strong background in computer architecture.
Strong background in compiler theory, algorithms, and optimization techniques.
SoC Project Leader
As an SoC Project Leader you will lead a team of engineers in the development of Zero ASIC’s leading edge products.
Drive the development of a chip product from definition, through RTL, design verification, physical implementation, and post silicon bringup.
Continuously refine the product architecture and implementation to derive a set of minimal features that meets the required goals for performance, flexibility, power, performance, cost, and ease of use.
Lead a distributed team of digital designers, physical designers, and software developers to drive the design to production.
Bachelor’s degree in Computer Science, Electrical Engineering, or related field.
10+ years of in advanced technology SoC design.
Proven track record full cycle development from planning to deployment.
Experience in all phases of design from architecture to post silicon bringup.
Multiple successful tape outs at 22nm and below.
Strong interpersonal, teamwork, and communication skills
Team leadership experience
Digital IC Designer
As a digital IC designer at Zero ASIC you will have the unique opportunity to drive design from inception all the way to production.
Drive the development of SoC blocks and subsystems from definition, through RTL, design verification, physical implementation, and post silicon bringup
Continuously refine the architecture and implementation to derive a set of minimal features that meets the required goals for performance, flexibility, power, performance, cost, and ease of use
Develop generators and automation frameworks to maximize future reuse potential
Collaborate with the physical design team and design verification team to design a high quality product that is optimized for power, speed, reliability, and ease of use
Collaborate with the application and post silicon bringup team to develop test vectors and driver software, ensuring that the block can be effectively used in the eventual SoC product
Bachelor’s degree in Computer Science, Electrical Engineering, or related field
Experience with micro-architecture development and RTL design
Strong grasp of computer architecture
Strong programming skills
Strong interpersonal, teamwork, and communication skills
Highly creative and self-driven
Senior Physical Design Engineer
As a senior physical designer you will develop highly automated design flows to reduce the barrier to silicon for everyone.
Lead the development of state of the art automated physical design methodologies.
Lead back-end SoC implementation efforts from RTL to tapeout/packaging.
Work effectively with RTL design team, firmware team, and customers on agile SoC development projects.
BS in EE/CE and 5+ years of experience (or equivalent) in SoC physical design.
Experience with multiple successful commercial tapeouts at advanced process nodes(16nm and below required, 7nm or smaller preferred).
Strong working knowledge of back-end tools and flows – floor planning, P&R, timing, power, EMIR, DFM, DFT, clocking, power grid analysis, thermal, physical verification, synthesis, and sign-off.
Experience with integration of complex high speed 3rd party mixed signal IP.
Strong programming and scripting skills (TCL, Python).
Strong communication skills.
Highly creative and self-driven.
Principal Software Engineer
This position serves as the software team lead for Zero ASIC’s unified software solution that integrates FPGA hardware model generation with a complete RTL-to-bitstream FPGA design automation flow. The Principal Software Architect will synthesize high-level FPGA hardware-software codesign requirements into a viable software product that can be deployed for end use by third parties.
Translate top level FPGA EDA software requirements into detailed requirements suitable for guiding production implementation.
Guide junior software engineers in FPGA EDA software implementation
Lead team code reviews, establish team best practices
Lead development of software documentation
Work closely with FPGA chip design team to ensure smooth handoff and tight integration
BS in Computer Science or Computer Engineering
10+ years of hands-on experience (professional and/or relevant academic research) in electronic design automation software development
Experience in deploying software products to the field
Experience leading small teams of software engineers
Strong background in Python and C++