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Career Opportunities

We are always looking for outstanding new team members. If you think you can help us lower the barrier to silicon, we encourage you to send a resume and intro to

Zero ASIC does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. Zero ASIC is an equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status.

Senior Verification Engineer

Senior Verification Engineer 

As Senior Verification Engineer, you will be responsible for development of Zero ASIC’s verification methodology, infrastructure and implementation. You will be a strong contributor on a small team focused on designing, fabricating, and testing Zero ASIC chiplets and SoCs.


  • Drive define and implementation of a holistic verification framework for multiple, diverse chips being designed in the team

  • Implement various verification environments using both commercial and open source tool suites, tailored to the needs of the different designs

  • Ensure high quality design for tapeout

  • Collaborate with the design and system team on product definitions 


  • Bachelor’s degree in Computer Science, Electrical Engineering, or related field

  • 10+ years of industry/academic experience in design verification 

  • Experience with verification tools, methodologies and implementation

  • Experience with formal verification

  • Strong programming/scripting skills

  • Strong interpersonal, teamwork, and communication skills

  • Highly creative and self-driven

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Digital IC Designer

As a digital IC designer at Zero ASIC you will have the unique opportunity to drive design from inception all the way to production.


  • Drive the development of SoC blocks and subsystems from definition, through RTL, design verification, physical implementation, and post silicon bringup

  • Continuously refine the architecture and implementation to derive a set of minimal features that meets the required goals for performance, flexibility, power, performance, cost, and ease of use

  • Develop generators and automation frameworks to maximize future reuse potential

  • Collaborate with the physical design team and design verification team to design a high quality product that is optimized for power, speed, reliability, and ease of use

  • Collaborate with the application and post silicon bringup team to develop test vectors and driver software, ensuring that the block can be effectively used in the eventual SoC product


  • Bachelor’s degree in Computer Science, Electrical Engineering, or related field

  • Experience with micro-architecture development and RTL design

  • Strong grasp of computer architecture

  • Strong programming skills

  • Strong interpersonal, teamwork, and communication skills

  • Highly creative and self-driven

Senior Physical Design Engineer

As a senior physical designer you will  develop highly automated design flows  to reduce the barrier to silicon for everyone.


  • Lead the development of state of the art automated physical design methodologies.

  • Lead back-end SoC implementation efforts from RTL to tapeout/packaging.

  • Work effectively with RTL design team, firmware team, and customers on agile SoC development projects.


  • BS in EE/CE and 5+ years of experience (or equivalent) in SoC physical design.

  • Experience with multiple successful commercial tapeouts at advanced process nodes(16nm and below required, 7nm or smaller preferred).

  • Strong working knowledge of back-end tools and flows – floor planning, P&R, timing, power, EMIR, DFM, DFT, clocking, power grid analysis, thermal, physical verification, synthesis, and sign-off.

  • Experience with integration of complex high speed 3rd party mixed signal IP.

  • Strong programming and scripting skills (TCL, Python).

  • Strong communication skills.

  • Highly creative and self-driven.

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Principal Software Engineer

This position serves as the software team lead for Zero ASIC’s unified software solution that integrates FPGA hardware model generation with a complete RTL-to-bitstream FPGA design automation flow.  The Principal Software Architect will synthesize high-level FPGA hardware-software codesign requirements into a viable software product that can be deployed for end use by third parties.


  • Translate top level FPGA EDA software requirements into detailed requirements suitable for guiding production implementation.

  • Guide junior software engineers in FPGA EDA software implementation

  • Lead team code reviews, establish team best practices

  • Lead development of software documentation

  • Work closely with FPGA chip design team to ensure smooth handoff and tight integration


  • BS in Computer Science or Computer Engineering

  • 10+ years of hands-on experience (professional and/or relevant academic research) in electronic design automation software development

  • Experience in deploying software products to the field

  • Experience leading small teams of software engineers

  • Strong background in Python and C++

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Machine Learning Software Engineer

As Machine Learning Software Engineer, you will contribute to the development of Zero ASIC’s machine learning solutions. You will be a strong contributor on a small team focused on designing, fabricating, and testing Zero ASIC devices.


  • Architect, design, and implement compiler support for Zero ASIC’s neural network inference platform

  • Develop and maintain ML compiler infrastructure, including benchmarking tools and automation scripts

  • Design and implement compiler optimizations for ML models

  • Work with hardware architects to improve the efficiency of system via software/hardware co-design

  • Stay up-to-date with the latest research and industry developments in the field of ML compilers.


  • BS/MS or PhD in Computer Science or related field

  • 3+ years of industry experience

  • Strong background in compiler theory, algorithms, and optimization techniques

  • Strong understanding of ML operators and their implementations

  • Familiarity with parallel computer architectures

  • Familiarity with machine learning frameworks such as TensorFlow, PyTorch, and ONNX

  • Knowledge of computer architectures used for neural network inference, and neural network performance characteristics is a plus

  • Experience in ML compilers and MLIR is a plus

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Software Engineer - Front End

Join the Zero ASIC team to lead front-end engineering for our new web platform, and make your mark on an exciting greenfield project.


  • Development of our application UI from conception to launch, including highly interactive user-experiences.

  • Shared operational ownership of the application, including documentation and support. 

  • Design consistency and evolution of our web properties.

  • Reusable UI components and style libraries.

  • Team growth and guidance in front-end architectural decisions.


  • Experience shipping software as a service (SaaS) products to users.

  • Experience leading small teams of software engineers.

  • BS in engineering or related field

  • Working experience with modern web technologies including:CSS (Tailwind)

  • Web UI Components (Svelte or React)

  • Web UI Frameworks and libraries for routing, data fetching 

  • Application dev tooling and processes (git, GitHub, CI/CD)

  •  Application deployment models (SSG, SSR, ISR)

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Senior Infrastructure Engineer

Join the Zero ASIC team to lead infrastructure engineering for an exciting new hosted platform.


  • Architecture and development of dynamically provisioned hosted services.

  • Automation, observability, and shared operational ownership of the platform.

  • Security of access control across corporate tenants.


  • Experience shipping software as a service (SaaS) products to users.

  • Working experience with major cloud providers (AWS, Azure, GCP).

  • Experience rolling out infrastructure as code tools (Kubernetes, Terraform, GitOps)

  • Application dev tooling and processes (git, GitHub, CI/CD)

  • Experience leading small teams of engineers.

  • BS in engineering or related field.

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Director of Advanced Packaging

As the director of advanced packaging you will lead the development of heterogeneous system-in-package architectures and partnerships to address high volume and long tail manufacturing needs.


  • Lead the development of novel package architectures and manufacturing flows for the company’s heterogeneous system in package approach.

  • Work with OSATs and other partners to bring solutions from concept to high volume manufacturing .

  • Recruit and manage a team of internal individual contributors and external consultants to support high volume manufacturing.      

  • Collaborate with the internal SoC design and architecture teams and external organization to define electrical, protocol, reliability, mechanical, and test standards for advanced packaging.

  • Collaborate with the SoC architecture and design team to converge on package architectures that 


  • PhD or Master’s Degree in the technical subject area.

  • 10+ years of experience in advanced semiconductor packaging

  • Experience with high volume SoC product manufacturing (>1M units)

  • Domain expertise in SoC reliability (ESD, EM, reliability, material compatibility, coplanarity controls, warpage mitigation, board interfaces).

  • Domain expertise in flip-chip, WLFO, 2.5D/3D, silicon interposers, advanced build up substrates, underfill, heatsinks, board.

  • Domain expertise in package signal integrity and power delivery, 

  • Demonstrated success in low product cost optimization through appropriately constraining architecture, materials, vendors.

  • Strong ties to the advanced packaging industry community.   

  • Outstanding collaboration skills

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