Zero ASIC releases Wildebeest, the world's highest performance FPGA synthesis tool.

Zero ASIC releases Wildebeest, the world’s highest performance FPGA synthesis tool.

Cambridge, MA – September 17, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of Wildebeest^TM, the world’s highest performance FPGA synthesis tool.

Background

The software world has largely moved away from proprietary, vendor-locked compilers in favor of open source alternatives such as LLVM¹ and GCC. Early on, these open source compilers lagged behind in performance, but over time, through the collective effort of the community, they caught up and even surpassed their proprietary counterparts.

In hardware, a similar transformation has been unfolding. Thanks to the pioneering work of Alan Mishchenko (ABC²), Claire Xenia Wolf (Yosys³), and the broader open source EDA community, FPGA developers have had access to a full-featured Verilog RTL synthesis toolchain for years. Recently, SystemVerilog support has since been added through Mike Popoloski’s excellent Slang parser⁴. Thanks to strong community involvement, the Yosys project now supports FPGA synthesis for a number of commercial and academic FPGA architectures.

Unfortunately, funding for open source FPGA synthesis has been minimal, and as a result a large QoR gap between open source and proprietary synthesis remains. Industrial users, who care obsessively about performance, have thus been stuck between a rock and a hard place: “Freedom or Performance”.

Attribute	Vendor Tool	Yosys
FPGA Support	Yes	No
Lock-in	Yes	No
Open Source	No	Yes
Free	Yes/No	Yes
Binary Size	Large	Small
QoR	Great	Good
Robustness	Great	Good

Wildebeest Intro

Wildebeest introduces a number of critical optimization techniques to open source. Some of these techniques are standard practice in commercial compilers, but this is the first time they have been demonstrated in an open source FPGA synthesis tool.

The most important Wildebeest strategy is the use of circuit size as a primary feature for selecting the synthesis algorithms. Existing single script solutions don’t work well because they either fail to converge for large circuits or sacrifice performance for robustness. Using a carefully selected set of size appropriate optimization scripts, Wildebeest achieves robustness and high performance for a wide range of benchmark (up to 1M LUT designs).

Another important aspect of the Wildebeest approach is the effective use of the most advanced abc9 commands for speculative synthesis and logic depth minimization. ABC is an incredibly powerful logic synthesis library, but making effective use of all commands is a non-trivial task that requires deep expertise in logic synthesis, the ABC architecture, and Yosys, and software development.

Logic optimization is only as good as the benchmark data that grounds the algorithms used. Wildebeest adopted an industrial approach to development from day one, developing an internal suite of 150+ carefully selected benchmarks and automated profiling utilities. The open source LogikBench benchmarks suite was created to enable independent evaluation and benchmarking.

Logic synthesis has been around for over 50 years. During this time, basic synthesis algorithms and approaches have been openly published by the synthesis R&D community, but many of the “outer loop” tricks of the trade have been kept hidden by practitioners within proprietary tools. The lead Wildebeest developer, Dr. Thierry Besson is an industry insider with 30 years of experience in developing state of the art commercial logic synthesis solutions. Dr. Besson has previously contributed the fastest/smallest results on a number of the EPFL logic synthesis benchmarks and with Wildebeest he is releasing many of these techniques into the wild.⁵

Benchmark Results

The table below shows how Wildebeest compares against both open-source and proprietary synthesis tools for the picorv32 CPU design. To run Wildebeest across a broader set of benchmarks, see the LogikBench project.

Device	Arch	Tool	Synthesis Command	LUTs	Logic Depth
z1060	LUT6	wildebeest	synth_fpga	2312	40
z1060	LUT6	wildebeest	synth_fpga -opt delay	2677	6
Vendor-1	LUT6	vendor	(proprietary)	2870	7
Vendor-2	LUT6	vendor	(proprietary)	2947	8
xc7	LUT6	yosys (0.56)	synth_xilinx -nocarry	3072	17
z1010	LUT4	wildebeest	synth_fpga	3593	39
z1010	LUT4	wildebeest	synth_fpga -opt delay	4112	8
ice40	LUT4	yosys (0.56)	synth_ice40 -dsp -nocarry	4378	33

The results show that Wildebeest QoR exceeds both proprietary and open source FPGA synthesis solutions.

Future Work

This initial Wildebeest release is only the beginning of the journey. The development team has a pipeline of optimization techniques in development with QoR that is expected to exceed current proprietary tools by a wide margin.

The long term goal of the Wildebeest project is to help bring forth an era of “LLVM for synthesis” by working with the community to develop high performance open source FPGA tools, robust standard IRs and file formats, and broad hardware vendor adoption.

Demo

To try out the Wildebeest, follow these installation instructions, download the picorv32 CPU example, launch yosys, and run the command sequence below.

plugin -i wildebeest
read_verilog picorv32.v
hierarchy -check -top picorv32
synth_fpga -partname z1010

Availability

The Wildebeest source code was officially released on September 17, 2025 and can be downloaded via github:

https://github.com/zeroasiccorp/wildebeest

About Zero ASIC

Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon through chiplets and design automation. Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.

References

C. Lattner, V. Adve, “LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation”, Proc. International Symposium on Code Generation and Optimization 2004 ↩
R. Brayton and A. Mishchenko, “ABC: An academic industrial-strength verification tool”, Proc. CAV 2010 ↩
C. Wolf, Johann Glaser., “Yosys - A Free Verilog Synthesis Suite”, Proc. Austrochip 2013 ↩
M. Popoloski, “Slang: a SystemVerilog Compiler”, https://github.com/MikePopoloski/slang ↩
EPFL Benchmark Suite Best Results, https://github.com/lsils/benchmarks/tree/master/best_results ↩