Logik
Logik is an open source FPGA toolchain that fully automates converting RTL to bits, including synthesis, placement, routing, bitstream generation, and analysis. Users enter design sources, constraints, and compile options through a simple SiliconCompiler Python API. Once setup is complete, automated compilation can be initiated with a single line run command.
Logik supports most of the features you would expect in a commercial proprietary FPGA tool chain.
| Feature | Status |
|---|---|
| Design languages | Verilog, SystemVerilog, VHDL |
| ALU synthesis | Supported |
| RAM synthesis | Supported |
| Timing constraints (SDC) | Supported |
| Pin Constraints (PCF) | Supported |
| Bitstream generation | Supported |
| IP management | Supported |
| Remote compilation | Supported |
| Multi-clock designs | In progress |
| FPGA devices | ZA |
To learn more about Logik, please see the GitHub repo.