Logik

Logik is an open source FPGA toolchain that fully automates converting RTL to bits, including synthesis, placement, routing, bitstream generation, and analysis. Users enter design sources, constraints, and compile options through a simple SiliconCompiler Python API. Once setup is complete, automated compilation can be initiated with a single line run command.

logik_flow

Logik supports most of the features you would expect in a commercial proprietary FPGA tool chain.

FeatureStatus
Design languagesVerilog, SystemVerilog, VHDL
ALU synthesisSupported
RAM synthesisSupported
Timing constraints (SDC)Supported
Pin Constraints (PCF)Supported
Bitstream generationSupported
IP managementSupported
Remote compilationSupported
Multi-clock designsIn progress
FPGA devicesZA

To learn more about Logik, please see the GitHub repo.