Zero ASIC completes FPGA, CPU, and SRAM testchips
Some of you may have been wondering why things have been quiet at ZeroASIC? The answer is that we have been busy working! 😀 I am very excited to tell you that we have now taped out 3 different homegrown chiplet designs in an advanced FinFET node: a multicore RISC-V CPU, a new FPGA architecture, and a large capacity memory. (All three chiplets were taped out in less than 24hrs using SiliconCompiler. https://lnkd.in/e4ya4K6i ). More information about Zero ASIC's platform and general availability will be announced in 2023.
If you are curious and want to find out more about our plans, send an email to [email protected]. We are still in stealth, but I hints are given on an individual basis.
Happy Holidays! 🎄 🕎
--Andreas Olofsson