EBRICK-CPU

Introduction

The EBRICK-CPU is a quad-core 64-bit RISC-V ISA, dual-issue, in-order application class processor chiplet implemented in 12nm.

Block diagram

Core Features

  • Quad-core RISC-V RV64GC cpu cluster
  • In-order dual-issue pipeline
  • 32KB L1 instruction cache
  • 32KB L1 data cache
  • 1MB L2 cache
  • L2 cache can be reconfigured as scratchpad
  • 3.6 CoreMarks/MHz
  • Up to 1.5GHz core operating frequency
  • On-chip general purpose DMA

Connectivity Features

ProtocolQuantity
CLINK (128gbps)4
UART2
I2C2
GPIO64
ETH 10/100/10001
SDIO1
SPI2
QSPI1
JTAG1
PWM1

Software Components

  • GCC
  • Linux
  • Yocto
  • A complete open source EBRICK-CPU SDK will be released upon device sampling.

Chiplet Dimensions

  • 2mm x 2mm

Status & Availability

StageStatus
Test ChipCompleted
EmulationAvailable
Device SamplingQ3, 2024
©2023 by Zero ASIC Corporation. All rights reserved.
Terms | Privacy