EBRICK-CPU
Introduction
The EBRICK-CPU is a quad-core 64-bit RISC-V ISA, dual-issue, in-order application class processor chiplet implemented in 12nm.
Block diagram
Core Features
- Quad-core RISC-V RV64GC cpu cluster
- In-order dual-issue pipeline
- 32KB L1 instruction cache
- 32KB L1 data cache
- 1MB L2 cache
- L2 cache can be reconfigured as scratchpad
- 3.6 CoreMarks/MHz
- Up to 1.5GHz core operating frequency
- On-chip general purpose DMA
Connectivity Features
Protocol | Quantity |
---|
CLINK (128gbps) | 4 |
UART | 2 |
I2C | 2 |
GPIO | 64 |
ETH 10/100/1000 | 1 |
SDIO | 1 |
SPI | 2 |
QSPI | 1 |
JTAG | 1 |
PWM | 1 |
Software Components
- GCC
- Linux
- Yocto
- A complete open source EBRICK-CPU SDK will be released upon device sampling.
Chiplet Dimensions
Status & Availability
Stage | Status |
---|
Test Chip | Completed |
Emulation | Available |
Device Sampling | Q3, 2024 |