Chiplet I/O Architect

Zero ASIC is seeking a chiplet I/O architect to lead the development of 2D, 2.5D, and 3D die-to-die interfaces the world’s first composable chiplet platform.

If interested, send your resume to [email protected].

Responsibilities

• Lead the development of high-efficiency die-to-die chiplet interfaces for our family of composable chiplets from architecture to production

• Design chiplet interfaces in multiple process nodes

• Interact with customers, design partners, and standards groups to refine interface specifications and architecture

• Collaborate with physical design and integration teams to guide package, board, and system development

• Lead pre-silicon and post-silicon post-silicon chiplet interface validation

• Mentor and provide technical leadership to engineering teams

Requirements

• BS in Electrical Engineering or related field

• 10+ years of experience in high-speed digital or mixed-signal interface design (e.g., SerDes, DDR, PCIe, or die-to-die)

• Hands-on experience with UCIe, BoW, AIB, or similar die-to-die implementations

• Deep understanding of link-layer and PHY-level architectures, clocking, timing closure, and signal integrity, etc.

• Outstanding programming skills (Verilog, Python, C++, …)

• Familiarity with packaging technologies such as 2.5D, 3D integration, and advanced interposers

• Experience with DFT, power management, and post-silicon validation

• Proven ability to drive cross-disciplinary efforts from early architecture through production

• Experience in leading technical projects