Memory System Architect

Zero ASIC is seeking a memory system architect to develop high performance memory interface chiplets for the world’s first composable chiplet platform.

If interested, send your resume to [email protected].

Responsibilities

• Lead the development of high speed memory interface chiplets from architecture to shipping products

• Interact with customers and incorporate feedback into the platform

• Lead the RTL implementation and pre-silicon verification/validation of the product

• Integrate externally licensed physical and controller IP as needed

• Collaborate with physical design, application teams, and manufacturing/test teams to bring products to market

• Mentor and provide technical leadership to engineering teams

Requirements

• BS in Computer Engineering, Electrical Engineering or related field

• 5+ years of applicable hands-on architrave and RTL experience in memory or CPU subsystems for ML ASICs or high performance CPUs

• Outstanding programming skills (Verilog, Python, C++, …)

• Strong first principle understanding of electronics (analog and digital)

• Experience in deploying silicon products

• Experience in leading technical projects