Tardigrade ASIC Logic Synthesis

Tardigrade^TM is a state of the art logic synthesis tool built for the era of AI assisted chip design.

Key Features

• No license token limits
• Production-ready elaboration for synthesizable SystemVerilog
• Timing driven logic optimization (with full SDC support)
• Advanced node tech mapping
• Up to 5x clock frequency boost compared to open source tools
• 1 GHz+ clock frequency timing closure
• Large capacity (>5M instances)
• Fast incremental timing optimization loops
• Standardized AI friendly QoR JSON metrics
• Cloud scale infrastructure via SiliconCompiler
• Transparent benchmarking via LogikBench

Benchmark Results

The following table illustrates timing improvements provided by Tardigrade on a set of representative circuits from the LogikBench RTL benchmark suite:

Benchmark Design	Yosys1	Tardigrade2	TG Boost
Picorv32 (with MULT)	314 MHz	1,280 MHz	4.07x
BlackParrot	168 MHz	870 MHz	5.17x
TPU	571 MHz	1,575 MHz	2.75x

Access Model

Tardigrade has already been used successfully by the internal Zero ASIC design team and while Tardigrade will never be a traditional commercial EDA product, Zero ASIC is open to discussing partnerships and/or royalty-free source code licenses.

Footnotes

1. Run via the stock SiliconCompiler Yosys flow and LambdaPDK asap7 PDK. Timing verified using the OpenSTA timing engine. All optimization and timing analysis is run in the slow (SS) corner. ↩

2. Run via Tardigrade using the LambdaPDK asap7 PDK. Timing signoff is identical to the setup in Note1. ↩