Network Architect
Zero ASIC is seeking a network architect to develop high performance networking chiplets for the world’s first composable chiplet platform.
If interested, send your resume to [email protected].
Responsibilities
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Lead the development of high speed networking chiplets from architecture to shipping product
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Interact with customers and incorporate feedback into the platform
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Lead the RTL implementation and pre-silicon verification/validation of the product
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Integrate externally licensed physical and controller IP as needed
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Collaborate with physical design and application teams to bring the product to market
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Mentor and provide technical leadership to engineering teams
Requirements
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BS in Computer Science, Computer Engineering, Electrical Engineering or related field
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5+ years of hands-on RTL design experience in designing I/O subsystems (memory or networking) for I/O ASICs, ML ASICs, high performance SoCs products
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Strong grasp of networking concepts (buffering, queuing, scheduling, standards, protocols, drivers)
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Outstanding programming skills (Verilog, Python, C++, …)
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First principle understanding of electronics (analog and digital)
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Experience in deploying silicon products
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Experience in leading technical projects