System I/O Architect

Zero ASIC is seeking a system I/O architect to develop high performance networking chiplets for the world’s first composable chiplet platform.

If interested, send your resume to [email protected].

Responsibilities

• Lead the development of high speed networking chiplets from architecture to shipping product

• Interact with customers and incorporate feedback into the platform

• Lead the RTL implementation and pre-silicon verification/validation of the product

• Integrate externally licensed physical and controller IP as needed

• Collaborate with physical design and application teams to bring the product to market

• Mentor and provide technical leadership to engineering teams

Requirements

• BS in Computer Science, Computer Engineering, Electrical Engineering or related field

• 5+ years of hands-on RTL design experience in designing I/O subsystems (memory or networking) for I/O ASICs, ML ASICs, high performance SoCs products

• Strong grasp of networking concepts (buffering, queuing, scheduling, standards, protocols, drivers)

• Outstanding programming skills (Verilog, Python, C++, …)

• First principle understanding of electronics (analog and digital)

• Experience in deploying silicon products

• Experience in leading technical projects