Principal Design Engineer (2 openings)

Zero ASIC is seeking veteran chip designers to join our team building a portfolio of composable chiplets and substrate fabrics.

If interested, send your resume to [email protected].

Responsibilities

• Lead the development of chiplets from definition, through RTL, pre-silicon validation, physical implementation, silicon bring-up, and customer shipments.

• Personally design high performance modules and sub-systems, leverating AI to maximize productivity.

• Contribute (some) RTL to the open source community.

• Contribute knowledge and code to train the next generation of designers and AI models.

• Participate in design reviews and contribute key insights from a career of product design experience.

• Mentor and provide technical leadership to junior engineers.

Requirements

• BS in Electrical Engineering or related field.

• 10+ years of experience in high performance SoC product development.

• Significant contribution to high volume SoC products.

• Significaint experience in high performance microarchitecture/RTl development in ONE (or more) of the following areas: NPUs, CPUs, NOCs, NICs, high speed serdes, GPUs, FPGAs, RISC-V development, ARM integration, memory subsystems, IO subsystems.

• Broad set of chip design skills.

• Experience in leading technical projects.