Logik
Logik is an open source FPGA tool chain with support for high level language parsing, synthesis, placement, routing, bitstream generation, and analysis. Users enter design sources, constraints, and compile options through a simple SiliconCompiler Python API. Once setup is complete, automated compilation can be initiated with a single line run command. Logik relies on the Logiklib project for all architecture and device descriptions.
Key Features
Logik supports most of the features you would expect in a commercial proprietary FPGA tool chain.
| Feature | Status |
|---|---|
| Design languages | SystemVerilog, Verilog, VHDL |
| DSP synthesis | Supported |
| RAM synthesis | Supported |
| Timing constraints (SDC) | Supported |
| Pin Constraints (PCF) | Supported |
| Bitstream generation | Supported |
| IP management | Supported |
| Remote compilation | Supported |
| Multi-clock designs | Supported |
| Supported devices | Logiklib devices |
To learn more about Logik, please visit the GitHub repo.