Wildebeest
The Wildebeest project is an open-source RTL synthesis tool that builds on the mature Yosys platform and extends it with advanced logic synthesis algorithms for state-of-the-art quality of results (QoR).
The project is initially focused on supporting Platypus FPGAs. However, most of the Platypus-specific optimization passes are general-purpose and can be easily adapted for other targets. The long-term goal of Wildebeest is to serve as a common hierarchical synthesis engine, providing a library of high-performance optimization passes that can be shared between targets. The groundwork for this effort has already begun with the introduction of the -config option.
The table below shows how Wildebeest compares against both open-source and proprietary synthesis tools on the picorv32 CPU design.
To run Wildebeest across a broader set of benchmarks, see LogikBench.
| Device | Arch | Tool | Synthesis Command | LUTs | Logic Depth |
|---|---|---|---|---|---|
| z1060 | LUT6 | wildebeest | synth_fpga | 2312 | 42 |
| z1060 | LUT6 | wildebeest | synth_fpga -opt delay | 2677 | 6 |
| Vendor-1 | LUT6 | vendor | (proprietary) | 2870 | 7 |
| Vendor-2 | LUT6 | vendor | (proprietary) | 2947 | 8 |
| xc7 | LUT6 | yosys (0.56) | synth_xilinx -nocarry | 3072 | 17 |
| z1010 | LUT4 | wildebeest | synth_fpga | 3593 | 39 |
| z1010 | LUT4 | wildebeest | synth_fpga -opt delay | 4112 | 8 |
| ice40 | LUT4 | yosys (0.56) | synth_ice40 -dsp -nocarry | 4378 | 33 |
NOTE: We made a best effort to isolate synthesis QoR from hardware-specific details (e.g., LUT4 vs. LUT6, presence or absence of carry cells). For Yosys, this required disabling carry cells to match the Platypus architecture, which does not yet support them.
To learn more about Wildebeest, please visit the GitHub repo.