Zero ASIC announces release of Platypus heterogeneous eFPGA
Today Zero ASIC announces the release of a new set of breakthrough open standard eFPGA cores with an advanced set of embedded BRAM and DSPs.
Zero ASIC
Democratizing silicon.
Composable Chiplets
Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.
Standardized chiplets
First demonstration of fully standardized chiplets, supporting O(m^n) system permutations (m=library size, n=substrate sockets).
Smart substrates
Active 3D silicon substrates that decople compute and networking, enabling LEGO like system composition.
World leading energy efficiency
Sub 0.1 pj/bit chiplet communication efficiency.
Design IP Generators
Our platform of scalable processor IP generators enable rapid per application generation of bespoke FPGAs, CPUs, NOCs, and DSPs to meet the most stringent system requirements.
Automated
Push button 100% automated IP generation.
Scalable
Performance scalable from edge to data-center.
Mature
Our IP generators have been used to tape out chips at 65nm, 28nm, 16nm, and 12nm.
Silicon Compiler
To lower the barrier to custom ASICs, Zero ASIC developed SiliconCompiler, an open source hardware compilation platform. The principles behind SiliconCompiler are documented in this 2022 DAC paper.
Battle tested
Silicon proven flows supporting a large set of open source and proprietary EDA tools and PDKs.
24 Hour Tapeout Cycles
Optimized cloud scale build infrastructure enable rapid design cycles.
Deterministic
Standardized manifests and design-as-code approach enable guarantee compilation determinism.
Open source
No lock in or hidden agendas!
Digital Twins
Our Switchboard digital twin platform enables near real-time emulation, allowing teams to optimize the system hardware and software before committing to costly manufacturing cycles. The methodology behind our approach is detailed in this scientific paper.
Fast
Our chiplet optimized digital twin platform enables an order of magnitude faster build and run times compared to leading commercial emulators.
Scalable
Our latency insensitive enable wafer scale designs and beyond.
Flexible
Standardized model interfaces facilitate seamless transitions between high-level models (e.g. QEMU), cycle-accurate RTL simulators (e.g. Verilator), and hardware-in-the-loop systems (e.g. AWS F1 FPGAs).
Reinventing ASIC design
Step 1: Emulate
Use Digital Twin platform to optimize hardware and software.
Step 2: Prototype
Build rapid chiplet based prototypes.
Step 3: Optimize
Optimize chiplet composition based on market feedback.
Step 4: Go To Market
Place a production purchase order and start manufacturing.
Profit!
Highlights from our Blog
View all posts »Zero ASIC releases Wildebeest, the world's highest performance FPGA synthesis tool.
Cambridge, MA – September 17, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of WildebeestTM, the world's highest performance open source FPGA synthesis tool. Wildebeest is the first open source logic synthesis solution with Quality of Results (QoR) comparable to proprietary vendor locked tools.
Open-source static timing analysis for FPGAs
Today Zero ASIC is announcing availability of a production-grade, open-source static timing analysis (STA) flow for FPGAs, enabling analysis of complex multi-clock designs for the open-source FPGA design community.
Building Composable Chiplets
Today I had the pleasure of giving a talk at the CHISIC (Chiplets Solutions for Custom IC Design) workshop in Boston. CHISIC focuses on providing insights and solutions related to chiplet technology and its application in custom IC design, specifically targeting the field of artificial intelligence. The workshop aims to help attendees learn about the latest advancements in chiplet architectures, connectivity, and associated design challenges.
Zero ASIC launches world's first open standard eFPGA product
Cambridge, MA – March 18, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced PlatypusTM, the world's first open standard eFPGA product. Platypus addresses a long standing critical issue of FPGA obsolescence and vendor lock that has put critical infrastructure at risk.
Composable chiplets
Composable chiplets represent a powerful new design approach with the potential of disrupting a large portion of the semiconductor market. This month I will be presenting ideas for how chiplets can be applied to a number of critical applications.
Switchboard, an Open Source High-Performance Communication Platform
Zero ASIC is thrilled to announce Switchboard, a high-performance open-source framework for communication between RTL simulations, FPGA emulations, Python, and C++. Switchboard makes it possible to simulate large hardware systems in a distributed fashion, using a wide variety of model types, and to interact with the modeled systems from popular software languages.
SiliconCompiler Launch!
The open source SiliconCompiler project we have been working on for a year is now officially live. I am so thankfully to my collaborators Noah Moroze and William Ransohoff for joining me on this journey! Check it out and tell me what you think. We soft launched over the weekend and at least the Twitterverse seemed to like it. We are at DAC in SF this week. If you are here, I hope to see you!